1. Field of the Invention
The invention relates to protective circuits for CMOS integrated circuits which prevent damage to the gate oxide of the CMOS transistors and which raise the magnitude of the input signal that will trigger the inherent SCR structure contained within CMOS integrated circuits to prevent SCR latchup.
2. Description of the Prior Art
One type of prior art protective circuit which has been used to protect the gate oxide of the field effective transistors within CMOS integrated circuits consists of first and second protective diodes which are poled with respect to an input terminal, a first power supply terminal and a second power supply terminal (ground or negative potential) so that the anode of the first diode is coupled to the input terminal and the cathode of the first diode is coupled to a first power supply terminal, the cathode of the second diode is coupled to the input terminal and the anode of the second diode is coupled to a second power supply terminal. This circuit has also been used in configurations where the second power supply terminal is negative with respect to ground.
This circuit effectively prevents damage caused by potentials such as noise which are applied to the gate oxide of the CMOS circuit elements during operation that are greater than the first power supply terminal potential or less than the second power supply terminal potential. However, this circuit has the disadvantage that the inherent npnp and pnpn SCR structure of CMOS circuits will be triggered at input potentials as low as 0.6 volts greater than the first power supply terminal potential or 0.6 volts less than the second power supply terminal potential. Triggering of the inherent CMOS circuit SCR causes latchup which normally can only be stopped by turning off the circuit.
The first protective diode, which has its anode coupled to the circuit input, forms a pnpn SCR with n channel MOSFETS which are diffused into a p type well that contains the n type source and drain electrodes for the n channel MOSFETS.
The second protective diode, which has its cathode coupled to the circuit input, forms a npnp SCR with p channel MOSFETS which have p type source and drain diffusions within the n channel substrate.
Application Ser. No. 12042, now U.S. Pat. No. 4,264,941 entitled "Protective Circuit for Insulated Gate Field Effect Transistor Integrated Circuits", which is also assigned to the assignee of this application, discloses a protective circuit, which is useful for preventing damage to the gate oxide of CMOS integrated circuits during "zap testing", having first and second bipolar transistors of opposite conductivity type which have their emitter to collector circuit connected respectively in parallel with first and second protective diodes. The circuit input is coupled to the anode of the first protective diode and the cathode of the second protective diode. The cathode of the first protective diode is coupled to the drain power supply and the anode of the second protective diode is connected to the source power supply.
The protective circuit disclosed in Ser. No. 12042 differs from the instant invention in that the protective transistors disclosed in Ser. No. 12042 are biased into conduction during reverse bias testing of the protective diodes. In the present invention, the protective transistors are biased into conduction during forward biasing of the protective diodes during circuit operation.